Power analysis of link level and end-to-end data protection in networks on chip
2005 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, 2005, 1770-1773 p.Conference paper (Refereed)
We provide a power analysis for the communication in the Nostrum NoC concluding that power consumption is dominated by the links between switches while the switches and network interfaces contribute with a mere few percent to the power consumption. Further we analyze link level low power encoding techniques with the conclusion, that they spend several times more power than no encoding at all, if normalized for the same performance, which is done by adjusting supply voltage and frequency. Data protection schemes also have the potential to reduce power if voltage levels can be reduced and certain faults can be tolerated. We experiment with link level and end-to-end data protection schemes. They only moderately increase power consumption and have indeed the potential to save power. However, this potential strongly depends on the application traffic patterns and fault models of future technology generations.
Place, publisher, year, edition, pages
2005. 1770-1773 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Electric network topology, Encoding (symbols)
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-43156DOI: 10.1109/ISCAS.2005.1464951ISI: 000232002401231ScopusID: 2-s2.0-33745715755OAI: oai:DiVA.org:kth-43156DiVA: diva2:448196
IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005; Kobe; 23 May 2005 through 26 May 2005;
QC 201110142011-10-142011-10-132011-10-14Bibliographically approved