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A power efficient flit-admission scheme for wormhole-switched networks on chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2005 (English)In: WMSCI 2005: 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Vol 4 / [ed] Callaos, N; Lesso, W; Palesi, M, 2005, 25-30 p.Conference paper, Published paper (Refereed)
Abstract [en]

Reducing power consumption is a main challenge when adopting a network as a global on-chip communication interconnect since the reduction in power dissipation should not at the expense of degrading the system performance. We investigate power in a wormhole-switched network with focus on the impact of flit-admission schemes, i.e., when and how the flits of packets are admitted into the network We have proposed a novel flit-admission scheme that shows significant shrink of the switch complexity while maintaining equivalent network performance. This paper investigates its influence in network power involving both switches and links. We conduct experiments on a 2D mesh network. The results show that our flit-admission scheme achieves significant power and area reduction without performance penalty. To our knowledge, our work is the first study of power dissipation on flit admission schemes.

Place, publisher, year, edition, pages
2005. 25-30 p.
Keyword [en]
power consumption, network-on-chip
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-43345ISI: 000243684900005Scopus ID: 2-s2.0-84867373574ISBN: 978-980-6560-56-7 (print)OAI: oai:DiVA.org:kth-43345DiVA: diva2:448247
Conference
9th World Multi-Conference on Systemics, Cybernetics and Informatics Location: Orlando, FL Date: JUL 10-13, 2005
Note

QC 20111014

Available from: 2011-10-14 Created: 2011-10-14 Last updated: 2012-09-21Bibliographically approved
In thesis
1. Using wormhole switching for networks on chip: feasibility analysis and microarchitecture adaptation
Open this publication in new window or tab >>Using wormhole switching for networks on chip: feasibility analysis and microarchitecture adaptation
2005 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

Network-on-Chip (NoC) is proposed as a systematic approach to address future System-on-Chip (SoC) design difficulties. Due to its good performance and small buffering requirement, wormhole switching is being considered as a main network flow control mechanism for on-chip networks. Wormhole switching for NoCs is challenging from NoC application design and switch complexity reduction.

In a NoC design flow, mapping an application onto the network should conduct a feasibility analysis in order to determine whether the messages’ timing constraints can be satisfied, and whether the network can be efficiently utilized. This is necessary because network contentions lead to nondeterministic behavior in message delivery. For wormhole-switched networks, we have formulated a contention tree model to accurately capture network contentions and reflect the concurrent use of links. Based on this model, the timing bounds of real-time messages can be derived. Furthermore, we have developed an algorithm to test the feasibility of real-time messages in the networks.

From the wormhole switch micro-architecture level, switch complexity should be minimized to reduce cost but with reasonable performance penalty. We have investigated the flit admission and flit ejection problems that concern how the flits of packets are admitted into and ejected from the network, respectively. For flit admission, we propose a novel coupling scheme which binds a flit-admission queue with an output physical channel. Our results show that this scheme achieves a reduction of up to 8% in switch area and up to 35% in switch power over other comparable solutions. For flit ejection, we propose a p-sink model which differs from a typical ideal ejection model in that it uses only p flit sinks to eject flits instead of p • v flit sinks as required by the ideal model, where p is the number of physical channels of a switch and v is the number of virtual channels per physical channel. With this model, the buffering cost of flit sinks only depends on p, i.e., is irrespective of v. We have evaluated the coupled flit-admission technique and p-sink model in a 2D 4 x 4 mesh network. In our experiments, they exhibit only limited performance penalties in some cases. We believe that these cost-effective models are promising candidates to be used in wormhole-switched on-chip networks.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. x, 46 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:5
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-562 (URN)
Presentation
(English)
Note
QC 20100524Available from: 2005-12-28 Created: 2005-12-28 Last updated: 2012-03-23Bibliographically approved

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Lu, Zhonghai

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