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A nNnocore/CMOS Hybrid System-on-Package (SoP) architecture for future nanoelectronic systems
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2006 (English)In: Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05), 2006, 365-368 p.Conference paper, Published paper (Refereed)
Abstract [en]

Recent results showed that when the minimum feature size used in semi-conductor device fabrication moves to sub nanometre scale, several physical and economic limits jeopardize the device behaviour, binary logic, and the lithography techniques currently used. To surpass this "brick-wall" and continue the Moore's Law forever, novel nano-electronic devices are becoming more popular and promising. But, interconnecting nano-devices into complex electronic systems has not yet been demonstrated. In this paper, we propose a Nanocore/CMOS Hybrid System-on-Package (SoP) architecture which is suitable for any emerging nanotechnology.

Place, publisher, year, edition, pages
2006. 365-368 p.
Keyword [en]
AET cell, error-tolerant, hybrid, system-on-package, nanocore, nanoelectronic
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-43327DOI: 10.1109/HDP.2005.251425ISI: 000239707000062Scopus ID: 2-s2.0-42749102765ISBN: 0-7803-9292-2 (print)OAI: oai:DiVA.org:kth-43327DiVA: diva2:448438
Conference
8th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP 06) Location: Shanghai Univ, Shanghai, PEOPLES R CHINA Date: JUN 27, 2005-JUN 30, 2006
Note

QC 20111017

Available from: 2011-10-17 Created: 2011-10-14 Last updated: 2014-11-06Bibliographically approved

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Weerasekera, RoshanLiu, JianZheng, Li-RongTenhunen, Hannu
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