A nNnocore/CMOS Hybrid System-on-Package (SoP) architecture for future nanoelectronic systems
2006 (English)In: Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05), 2006, 365-368 p.Conference paper (Refereed)
Recent results showed that when the minimum feature size used in semi-conductor device fabrication moves to sub nanometre scale, several physical and economic limits jeopardize the device behaviour, binary logic, and the lithography techniques currently used. To surpass this "brick-wall" and continue the Moore's Law forever, novel nano-electronic devices are becoming more popular and promising. But, interconnecting nano-devices into complex electronic systems has not yet been demonstrated. In this paper, we propose a Nanocore/CMOS Hybrid System-on-Package (SoP) architecture which is suitable for any emerging nanotechnology.
Place, publisher, year, edition, pages
2006. 365-368 p.
AET cell, error-tolerant, hybrid, system-on-package, nanocore, nanoelectronic
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-43327DOI: 10.1109/HDP.2005.251425ISI: 000239707000062ScopusID: 2-s2.0-42749102765ISBN: 0-7803-9292-2OAI: oai:DiVA.org:kth-43327DiVA: diva2:448438
8th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP 06) Location: Shanghai Univ, Shanghai, PEOPLES R CHINA Date: JUN 27, 2005-JUN 30, 2006
QC 201110172011-10-172011-10-142014-11-06Bibliographically approved