Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
2005 (English)In: Norchip 2005, Proceedings, 2005, 200-205 p.Conference paper (Refereed)
As the dimensions of ASICs shrink down to the nanometer regime, the variability of the process parameters will increase. This variability threatens to make it extremely difficult to distribute a synchronous clock. all over the chip. Another option would be to replace critical synchronous parts with asynchronous counterparts with the same functionality. The main problems are, first, there is no established tool-flow that makes it easy for a designer to design an asynchronous circuits, and, second, there are no established design automation tools, except a few experimental ones. In addition, most designers today are trained to design synchronous circuits and have to be retrained. In this paper we present a method that solves all three of these problems, i.e., it allows a designer to start in the synchronous domain, and then automatically transform the synchronous representation of the circuit into an asynchronous one.
Place, publisher, year, edition, pages
2005. 200-205 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-43310ISI: 000241010100049ScopusID: 2-s2.0-33847302608ISBN: 1-4244-0064-3OAI: oai:DiVA.org:kth-43310DiVA: diva2:448530
23rd Norchip Conference Location: Oulu, FINLAND Date: NOV 21-22, 2005
QC 201110172011-10-172011-10-142011-10-17Bibliographically approved