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Pipelined DAC architecture using gray coding
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2005 (English)In: Norchip 2005, Proceedings, 2005, 141-144 p.Conference paper, Published paper (Refereed)
Abstract [en]

This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency. This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency.

Place, publisher, year, edition, pages
2005. 141-144 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-43308ISI: 000241010100034Scopus ID: 2-s2.0-33847232914ISBN: 1-4244-0064-3 (print)OAI: oai:DiVA.org:kth-43308DiVA: diva2:448553
Conference
23rd Norchip Conference Location: Oulu, FINLAND Date: NOV 21-22, 2005
Note
QC 20111017Available from: 2011-10-17 Created: 2011-10-14 Last updated: 2011-10-17Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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  • vancouver
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More styles
Language
  • de-DE
  • en-GB
  • en-US
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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