A modified cascaded sigma-delta modulator with improved linearity
2005 (English)In: IEEE Computer Society Annual Symposium on VLSI, Proceedings: NEW FRONTIERS IN VLSI DESIGN / [ed] Smailagic, A; Ranganathan, N, 2005, 77-82 p.Conference paper (Refereed)
This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10 MHz. The proposed modulator architecture employs the 2(nd) order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A Data-Weighted-Averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.
Place, publisher, year, edition, pages
2005. 77-82 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-43296DOI: 10.1109/ISVLSI.2005.10ISI: 000229610600013ScopusID: 2-s2.0-26844525099ISBN: 0-7695-2365-XOAI: oai:DiVA.org:kth-43296DiVA: diva2:448570
21st International Symposium on Lepton and Photon Interactions at High Energies Location: Batavia, IL Date: AUG 11-16, 2003
QC 201110172011-10-172011-10-142012-10-02Bibliographically approved