Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
2004 (English)In: ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, NEW YORK: IEEE , 2004, 748-751 p.Conference paper (Refereed)
This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT in a significantly shorter time compared to the previous methods. The quality of results is improved by enabling LUT re-implementation and by introducing a cost function which encourages input sharing among LUTs. The experimental results show that, on average, the presented algorithm computes 15.5% and 3.5% smaller LUT mappings compared to the ones obtained by FlowNlap and CutMap, respectively, using two orders of magnitude less CPU time. The speed of Hermes makes it suitable for running in an incremental manner during logic synthesis.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 748-751 p.
, ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-44013DOI: 10.1109/ICCAD.2004.1382676ISI: 000225494400110ScopusID: 2-s2.0-16244401635OAI: oai:DiVA.org:kth-44013DiVA: diva2:449071
International Conference on Computer Aided Design (ICCAD 2004). San Jose, CA. NOV 07-11, 2004
QC 201005252011-10-192011-10-192016-05-09Bibliographically approved