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Thermal-issues for design of high power SiC MESFETs
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-8108-2631
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-5845-3032
2004 (English)In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, 331-335 p.Conference paper, Published paper (Refereed)
Abstract [en]

Silicon carbide (SiC) power MESFETs have found application in RF source and power amplifiers for wireless telecommunication systems, phased-array radar systems, and other applications. SiC MESFETs can handle much higher power than silicon and gallium arsenide power devices, due to its superior material properties, including high critical electrical field, high electron saturation velocity, and high thermal conductivity. Despite the high thermal conductivity of the material, SiC power devices may suffer from severe self-heating when operating at very high power levels. In this report, the effect of self-heating on DC performance of SiC MESFETs with 1, 2, and 3 gate fingers were studied through 2D electro-thermal simulations using ISE-TOAD. The reduction in drain current caused by self-heating was found to be more prominent for transistors with more fingers and it imposes a limitation on both the output power and the power density (in W/mm) of multi-fingered large area devices. Thermal simulations have been performed using FEMLAB to predict the junction temperature of a MESFET with 1.5 mm gate periphery and a power dissipation of 4.5 W. Three different finger layouts were examined in terms of junction temperature, yield, and the ease and cost for fabrication of the devices. Thermal simulations were also done for a larger area MESFET with a gate periphery of 12 mm and power dissipation as high as 36 W. Three different ways to place the unit cell were studied. The effect of the thermal resistance between the die backside and the environment on the junction temperature was analyzed. The thermal resistance of the die itself was deduced. It was found that the packaging thermal resistance is usually much larger than the die thermal resistance. A couple of useful ways to reduce the packaging thermal resistance and the self-heating are also discussed.

Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 331-335 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-44323DOI: 10.1109/HPD.2004.1346722ISI: 000224594800061Scopus ID: 2-s2.0-14844303971ISBN: 0-7803-8620-5 (print)OAI: oai:DiVA.org:kth-44323DiVA: diva2:451105
Conference
6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP 04) Location: Shanghai, PEOPLES R CHINA Date: JUN 30-JUL 03, 2004
Note
QC 20111024Available from: 2011-10-24 Created: 2011-10-20 Last updated: 2011-10-24Bibliographically approved

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Zetterling, Carl-Mikael

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