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Low-power and error coding for network-on-chip traffic
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, 20-23 p.Conference paper, Published paper (Refereed)
Abstract [en]

The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.

Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 20-23 p.
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-44774ISI: 000227801500004Scopus ID: 2-s2.0-21244460341ISBN: 0-7803-8510-1 (print)OAI: oai:DiVA.org:kth-44774DiVA: diva2:451302
Conference
22nd Norchip Conference Location: Oslo, NORWAY Date: NOV 08-09, 2004
Note

QC 20111025

Available from: 2011-10-25 Created: 2011-10-25 Last updated: 2016-12-16Bibliographically approved

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Vitkovski, ArsenijHaukilahti, RaimoJantsch, AxelNilsson, Erland
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