Low-power and error coding for network-on-chip traffic
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, 20-23 p.Conference paper (Refereed)
The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 20-23 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-44774ISI: 000227801500004ScopusID: 2-s2.0-21244460341ISBN: 0-7803-8510-1OAI: oai:DiVA.org:kth-44774DiVA: diva2:451302
22nd Norchip Conference Location: Oslo, NORWAY Date: NOV 08-09, 2004
QC 201110252011-10-252011-10-252011-11-02Bibliographically approved