Chip-package co-design for high performance and reliability off-chip communications
2004 (English)In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, 31-36 p.Conference paper (Refereed)
Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design methodology is presented. We address high performance and reliability enhancement for off-chip communications under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, it is shown that the system-level performances such as signal integrity, bandwidth, and reliability are significantly improved through this co-design methodology.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 31-36 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-44729DOI: 10.1109/HPD.2004.1346669ISI: 000224594800008ScopusID: 2-s2.0-14844331476ISBN: 0-7803-8620-5OAI: oai:DiVA.org:kth-44729DiVA: diva2:451519
6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP 04) Location: Shanghai, PEOPLES R CHINA Date: JUN 30-JUL 03, 2004
QC 201110262011-10-262011-10-252012-02-14Bibliographically approved