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Chip-package co-design for high performance and reliability off-chip communications
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, 31-36 p.Conference paper, Published paper (Refereed)
Abstract [en]

Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design methodology is presented. We address high performance and reliability enhancement for off-chip communications under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, it is shown that the system-level performances such as signal integrity, bandwidth, and reliability are significantly improved through this co-design methodology.

Place, publisher, year, edition, pages
NEW YORK: IEEE , 2004. 31-36 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-44729DOI: 10.1109/HPD.2004.1346669ISI: 000224594800008Scopus ID: 2-s2.0-14844331476ISBN: 0-7803-8620-5 (print)OAI: oai:DiVA.org:kth-44729DiVA: diva2:451519
Conference
6th IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP 04) Location: Shanghai, PEOPLES R CHINA Date: JUN 30-JUL 03, 2004
Note
QC 20111026Available from: 2011-10-26 Created: 2011-10-25 Last updated: 2012-02-14Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
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  • de-DE
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