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Design and analysis of a self-timed duplex communication system
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 53, no 7, 798-814 p.Article in journal (Refereed) Published
Place, publisher, year, edition, pages
2004. Vol. 53, no 7, 798-814 p.
Keyword [en]
asynchronous circuits, communication protocols, modeling, Petri nets, power and pin efficiency, self-timed circuits, signal transition graphs, synthesis
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-41834DOI: 10.1109/TC.2004.26ISI: 000221406600002Scopus ID: 2-s2.0-3242655678OAI: oai:DiVA.org:kth-41834DiVA: diva2:453791
Note
QC 20111103Available from: 2011-11-03 Created: 2011-10-03 Last updated: 2017-12-08Bibliographically approved

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