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A network on chip architecture and design methodology
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
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2002 (English)In: VLSI 2002: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN, IEEE conference proceedings, 2002, 105-112 p.Conference paper (Refereed)
Abstract [en]

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2002. 105-112 p.
Keyword [en]
Communication switching, Computer architecture, Concrete, Design methodology, Field programmable gate arrays, Hardware, Network-on-a-chip, Packet switching, Shape, Switches
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-46709DOI: 10.1109/ISVLSI.2002.1016885ISI: 000176274900019ISBN: 0-7695-1486-3OAI: diva2:454023
IEEE Computer Society Annual Symposium on VLSI, 2002

© 2002 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. QC 20111115

Available from: 2011-11-15 Created: 2011-11-04 Last updated: 2012-11-21Bibliographically approved
In thesis
1. Architectural Techniques for Improving Performance in Networks on Chip
Open this publication in new window or tab >>Architectural Techniques for Improving Performance in Networks on Chip
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The main aim of this thesis is to propose enhancing techniques for the performance in Networks on Chips. In addition, a concrete proposal for a protocol stack within our NoC platform Nostrum is presented. Nostrum inherently supports both Best Effort as well as Guaranteed Throughput traffic delivery. It employs a deflective routing scheme for best effort traffic delivery that gives a small footprint of the switches in combination with robustness to disturbances in the network. For the traffic delivery with hard guarantees a TDMA based scheme is used. During the transmission process in a NoC several stages are involved. In the papers included, I propose a set of strategies to enhance the performance in several of these stages. The strategies are summarised as follows

Temporally Disjoint Networks is that a physical network, potentially, can be seen to contain a set of separate networks that a packet can enter dependenton when it enters the physical network. This has the consequence that wecould have different traffic types in the different networks.

Looped containers provide means to set up virtual circuits in networksusing deflective routing. High priority container packets are inserted intothe network to follow a predefined, closed, route between source and destination.At sender side the packets are loaded and sent to the destination where it is unloaded and sent back.

Proximity Congestion Awareness reduces the load of the network by diverting packets away from congested areas. It can increase the maximum trafficload by a factor of 20.

Dual Packet Exit increases the exit bandwidth of the network leading to a50 percent reduction in worst-case latency and a 30 percent reduction inaverage latency as well as a lowered buffer usage.

Priority Based Forced Requeue prematurely lifts out low priority packetsfrom the network to be requeued. Packets that have not yet entered the network compete with packets inside the network which gives tighter boundson admission with a reduction of worst case latencies by 50 percent.

Furthermore, Operational Efficiency is proposed as a measure to quantifyhow effective a network is and is defined as the throughput per buffers used in the system. An increase of the injection of packets into the network to increase the system throughput will have a cost associated to it and can be optimised to save energy.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xxiv, 103 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 11:13
National Category
Communication Systems
urn:nbn:se:kth:diva-48243 (URN)978-91-7501-169-1 (ISBN)
Public defence
2011-12-08, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:00 (English)
QC 20111124Available from: 2011-11-24 Created: 2011-11-16 Last updated: 2012-01-16Bibliographically approved

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