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Robustness enhancement through chip-package co-design for high-speed electronics
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: ISQED 2004:  , LOS ALAMITOS: IEEE COMPUTER SOC , 2004, 184-189 p.Conference paper, Published paper (Other academic)
Abstract [en]

Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design flow is presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, co-design can reduce signal integrity problem, enhance its bandwidth, and improve high-speed electronic systems robustness.

Place, publisher, year, edition, pages
LOS ALAMITOS: IEEE COMPUTER SOC , 2004. 184-189 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-47398ISI: 000221356900031Scopus ID: 2-s2.0-2942640148OAI: oai:DiVA.org:kth-47398DiVA: diva2:454898
Conference
5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS
Note
QC 20111108Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2012-02-14Bibliographically approved

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