Robustness enhancement through chip-package co-design for high-speed electronics
2004 (English)In: ISQED 2004: , LOS ALAMITOS: IEEE COMPUTER SOC , 2004, 184-189 p.Conference paper (Other academic)
Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design flow is presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, co-design can reduce signal integrity problem, enhance its bandwidth, and improve high-speed electronic systems robustness.
Place, publisher, year, edition, pages
LOS ALAMITOS: IEEE COMPUTER SOC , 2004. 184-189 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-47398ISI: 000221356900031ScopusID: 2-s2.0-2942640148OAI: oai:DiVA.org:kth-47398DiVA: diva2:454898
5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS
QC 201111082011-11-082011-11-082012-02-14Bibliographically approved