A Boolean Cube to VHDL converter and its application to parallel CRC generation
Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
The primary outcome of this thesis is found in three contributions. First, we developed an automatic converter from the cube representation of incompletely specified multiple-output Boolean function, given in Espresso format, to VHDL. The converter is designed specifically for updating functions of Feedback Shift Register (FSRs) in the Galois configuration, namely it reads in the description of a combinatorial function and adds register stages to the appropriate positions. The converter can handle both, Linear and Non-Linear feedback Shift Registers.
The second contribution is modifying the automatic converter to design a tool which gives the user the opportunity to see the hardware characteristics of its circuit quickly from the espresso format of its design.
The third contribution is applying the resulting converter to evaluate the results of the CRC generation algorithm presented in . We computed the hardware characteristics such as area, timing and power dissipation on most popular CRCs in ASIC and FPGA technologies.
Furthermore, we introduced a simple interface used to provide the user a good estimation of the power diagram during the executing time which is similar to probing the current of the circuit.
Place, publisher, year, edition, pages
2011. , 76 p.
ASIC, LFSR, NLFSR, Espresso, Parallel CRC, TCL, VHDL, FPGA, design compiler, ModelSim, Xilinx, Altera
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-48493OAI: oai:DiVA.org:kth-48493DiVA: diva2:457751
Subject / course
2011-09-16, Castor conference, Isafjordsgatan 39, Forum, 8th floor, Elevator C, Kista/ Stockholm, 01:34 (English)
Dubrova, Elena, Professor
Dubrova, Elena, Proffisor