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An Improved Hierarchical Design Flow for Coarse Grain Regular Fabrics
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This project included two parts. First, a reconfigurable cell was designed as the DataPath Unit (DPU) of a Dynamically Reconfigurable Resource Array (DRRA). In this cell, hardware resources were shared to be reused in different configurations. Consequently, the area was reduced by 68% in comparison with the previous DPU with the same functionality. It also demonstrated better performance at 1GHz.

Second, we implemented a DRRA fabric consisting of 150 coarse grain blocks using an improved hierarchical design flow presented in this project. We reused pre-synthesized sub-modules to eliminate the top-level synthesis thereby decreasing the logic synthesis process run-time by 92%. Also the pre-placed and routed sub-modules were reused as hard macros during the physical synthesis to reduce the design complexity which resulted in speeding up the design procedure significantly.

During the routing process, a regular manual routing approach was used. In order to exploit net regularity while routing, we developed a package to extract top-level fabric interconnection regularity, recognize the representative design unit to be routed manually, and propagate the routing to the entire chip. The representative design unit was routed by employing a two-stage approach, global routing followed by detailed routing while considering the congestion overflow and design rules.

By enabling reusability and exploiting regularity in the proposed hierarchical design flow, the design complexity becomes more manageable and designer can improve the design quality by focusing on only a small and critical part of the design instead of the whole system. Furthermore, using this routing methodology a pattern is replicated across the chip. Therefore, the cost of mask design during fabrication process is decreased. Also it results in timing uniformity and predictability across the chip. Although the total wire-length increased by 5%, a considerable decrease in number of wire segments and vias was observed which results in less parasitic capacitance and better manufacturability.

Place, publisher, year, edition, pages
2011. , 87 p.
Trita-ICT-EX, 163
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-48828OAI: diva2:458646
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2011-11-23 Created: 2011-11-23 Last updated: 2011-11-23Bibliographically approved

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