A Coarse-Grained Reconfigurable Protocol Processor
2011 (English)In: International Symposium on System-on-Chip, 2011. Proceedings, 2011Conference paper (Refereed)
Trade-off between flexibility and performance became an important factor for characterizing modern protocol processing architectures. While some solutions tend to be more flexible and less computational efficient like GPPs, other solutions like custom ASIC devices provide high computational efficiency while loosing the ability to cope with the diversity of current and evolving protocols. We propose a reconfigurable protocol processor that is flexible and highly adaptable to the needs of the required protocol with the ability to operate individually or as a multi-core integrating processors. We show how a common protocol processing task that consumes one third of RISC CPU time can be performed on our processor at high speed and low energy cost.
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IdentifiersURN: urn:nbn:se:kth:diva-49153DOI: 10.1109/ISSOC.2011.6089688ScopusID: 2-s2.0-83755188115OAI: oai:DiVA.org:kth-49153DiVA: diva2:459309
The 13th Annual SoC Event in Tampere
QC 201112192011-11-252011-11-252011-12-19Bibliographically approved