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A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receivers
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2010 (English)In: 23rd IEEE International SOC Conference, SOCC 2010, 2010, 413-416 p.Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a flexible timing circuit with 1.1ns delay resolution for energy detection IR-UWB receivers. Referenced at 900MHz input clock, the circuit generates multi-phased integration windows and reset signals that enable/disable the operation of analog blocks. The design is highly programmable, adapting the receiver to pulse level synchronization, symbol level synchronization, different data rates and various channel environments. Mixed-signal design flow is adopted to avoid the complexity of full custom design and the large power consumption of full synthesized digital design. The timing circuit is implemented in UMC 90nm CMOS process, with 219 #x03BC;W power consumption and 190*295 #x03BC;m2 die area.

Place, publisher, year, edition, pages
2010. 413-416 p.
Keyword [en]
CMOS;energy detection IR-UWB receivers;mixed-signal design flow;mixed-signal timing circuit;multiphased integration windows;power 219 muW;pulse level synchronization;reset signals;size 90 nm;symbol level synchronization;CMOS integrated circuits;mixed analogue-digital integrated circuits;radio receivers;synchronisation;timing circuits;ultra wideband communication;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-49207DOI: 10.1109/SOCC.2010.5784668Scopus ID: 2-s2.0-79960743674ISBN: 978-142446683-2 (print)OAI: oai:DiVA.org:kth-49207DiVA: diva2:459401
Conference
23rd IEEE International SOC Conference, SOCC 2010; Las Vegas, NV; United States; 27 September 2010 through 29 September 2010;
Note

QC 20150714

Available from: 2011-11-25 Created: 2011-11-25 Last updated: 2016-11-11Bibliographically approved
In thesis
1. Sub-Nyquist Sampling Impulse Radio UWB Receivers for the Internet-of-Things
Open this publication in new window or tab >>Sub-Nyquist Sampling Impulse Radio UWB Receivers for the Internet-of-Things
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In the era of Internet-of-Things, the demand for short range wireless links featured by low-power and low-cost, robust communication and high-precision positioning is growing rapidly. Impulse Radio Ultra-Wideband (IR-UWB) technology characterized by the transmission of sub-nanosecond pulses spanning up to several GHz band with extremely low power spectral density emerges as a promising candidate. Nevertheless, several challenges must be confronted in order to take the full advantage of IR-UWB technology. The most significant one lies in the reception of UWB signals. Traditional receiver requires Nyquist rate ADC which is overwhelmingly complex and power hungry. This dissertation proposes and investigates possible sub-Nyquist sampling techniques for IR-UWB receiver design.

In the first part of this dissertation, the IR-UWB receiver based on energy detection (ED) principle is explored. A low-power ED receiver featured by flexibility and multi-mode operation is proposed. The receiver prototype for 3-5 GHz band is implemented in 90 nm CMOS. Measurement results demonstrate that 16.3 mW power consumption and -79 dBm sensitivity at 10 Mb/s data rate can be achieved. To further optimize the receiver performance, threshold optimization is suggested for the on-off-keying modulated signal, and adaptive synchronization and integration region optimization is proposed. Finally, a low complexity burst packet detection scheme is proposed, which is adaptive to the variations of noise background and link distance.

In the second part of this dissertation, the IR-UWB receiver based on compressed sensing (CS) theory is investigated. Firstly, appropriate sparse basis, sensing matrix and reconstruction algorithms are suggested for the CS based IR-UWB receiver. And then, the architectural analysis of the CS receiver with focuses on the random noise processes in the CS measurement procedure is presented. At last, a novel two-path noise-reducing architecture for the CS receiver is proposed. Besides the improvement on the receiver performance, the proposed architecture also relaxes the hardware implementation of the CS random projection as well as the back-end signal reconstruction.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. 79 p.
Series
TRITA-ICT, 2016:23
Keyword
Ultra-Wideband, impulse radio, receiver, energy detection, compressed sensing, sub-Nyquist sampling, Internet-of-Things
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-195816 (URN)978-91-7729-174-9 (ISBN)
Public defence
2016-12-12, Sal 205, Electrum, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20161110

Available from: 2016-11-10 Created: 2016-11-09 Last updated: 2016-11-10Bibliographically approved

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