Mismatch aware power and area optimization of successive-approximation ADCs
2010 (English)In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 2010, 882-885 p.Conference paper (Other academic)
In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it is able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch. As a case study, a low power 12 bits SAR ADC has been designed in 0.18 #x03BC;m CMOS process, with 1-100 kHz sample rate.
Place, publisher, year, edition, pages
2010. 882-885 p.
CMOS process;area optimization;area-constrained ADC;device mismatch;device noise;low power ADC;mismatch aware power;power dissipations;process mismatch;quantization noise;size 0.18 mum;successive approximation register analog-digital converter;successive-approximation ADC;unit capacitor area size;word length 12 bit;CMOS integrated circuits;analogue-digital conversion;integrated circuit noise;low-power electronics;power aware computing;
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-49206DOI: 10.1109/ICECS.2010.5724653ScopusID: 2-s2.0-79953091090OAI: oai:DiVA.org:kth-49206DiVA: diva2:459404
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010. Athens. 12 December 2010 - 15 December 2010
QC 201111302011-11-252011-11-252016-04-12Bibliographically approved