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Mismatch aware power and area optimization of successive-approximation ADCs
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2010 (English)In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 2010, 882-885 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it is able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch. As a case study, a low power 12 bits SAR ADC has been designed in 0.18 #x03BC;m CMOS process, with 1-100 kHz sample rate.

Place, publisher, year, edition, pages
2010. 882-885 p.
Keyword [en]
CMOS process;area optimization;area-constrained ADC;device mismatch;device noise;low power ADC;mismatch aware power;power dissipations;process mismatch;quantization noise;size 0.18 mum;successive approximation register analog-digital converter;successive-approximation ADC;unit capacitor area size;word length 12 bit;CMOS integrated circuits;analogue-digital conversion;integrated circuit noise;low-power electronics;power aware computing;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-49206DOI: 10.1109/ICECS.2010.5724653Scopus ID: 2-s2.0-79953091090OAI: oai:DiVA.org:kth-49206DiVA: diva2:459404
Conference
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010. Athens. 12 December 2010 - 15 December 2010
Note
QC 20111130Available from: 2011-11-25 Created: 2011-11-25 Last updated: 2016-04-12Bibliographically approved
In thesis
1. Radio and Sensor Interfaces for Energy-autonomous Wireless Sensing
Open this publication in new window or tab >>Radio and Sensor Interfaces for Energy-autonomous Wireless Sensing
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Along with rapid development of sensing and communication technology, Internet of Things (IoTs) has enabled a tremendous number of applications in health care, agriculture, and industry. As the fundamental element, the wireless sensing node, such as radio tags need to be operating under micro power level for energy autonomy. The evolution of electronics towards highly energy-efficient systems requires joint efforts in developing innovative architectures and circuit techniques. In this dissertation, we explore ultra-low power circuits and systems for micropower wireless sensing in the context of IoTs, with a special focus on radio interfaces and sensor interfaces. The system architecture of UHF/UWB asymmetric radio is introduced firstly. The active UWB radio is employed for the tag-to-reader communication while the conventional UHF radio is used to power up and inventory the tag. On the tag side, an ultra-low power, high pulse swing, and power scalable UWB transmitter is studied. On the reader side, an asymmetric UHF/UWB reader is designed. Secondly, to eliminate power-hungry frequency synthesis circuitry, an energy-efficient UWB transmitter with wireless clock harvesting is presented. The transmitter is powered by an UHF signal wirelessly and respond UWB pulses by locking-gating-amplifying the sub-harmonic of the UHF signal. 21% locking range can be achieved to prevent PVT variations with -15 dBm injected power. Finally, radio-sensing interface co-design is explored. Taking the advantage of RC readout circuit and UWB pulse generator, the sensing information is directly extracted and transmitted in the time domain, exploiting high time-domain resolution UWB pulses. It eliminates the need of ADC of the sensor interface, meanwhile, reduces the number of bits to be transmitted for energy saving. The measurement results show that the proposed system exhibits 7.7 bits ENOB with an average relative error of 0.42%.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2016. xviii, 93 p.
Keyword
Ultra-wideband, asymmetric UHF/UWB radio, clock harvesting, time-domain sensing, energy efficiency, Internet-of-things
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-184851 (URN)978-91-7595-855-2 (ISBN)
Public defence
2016-05-02, Sal/hall B, Electrum, KTH-ICT, Kista, Kista, 13:30 (English)
Opponent
Supervisors
Funder
VINNOVA
Note

QC 20160412

Available from: 2016-04-12 Created: 2016-04-05 Last updated: 2016-04-18Bibliographically approved

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