Predicting bus contention effects on energy and performance in multi-processor SoCs
2011 (English)In: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, 1196-1199 p.Conference paper (Other academic)
Place, publisher, year, edition, pages
2011. 1196-1199 p.
algorithmic specification;bus contention effect prediction;gate-level estimation;multiprocessor SoC;microprocessor chips;system-on-chip;
IdentifiersURN: urn:nbn:se:kth:diva-49325ScopusID: 2-s2.0-79957550145OAI: oai:DiVA.org:kth-49325DiVA: diva2:459515
Design, Automation and Test in Europe, DATE. Grenoble. 14 March 2011 - 18 March 2011
QC 201111292011-11-252011-11-252011-11-29Bibliographically approved