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A general approach to high-level energy and performance estimation in system-on-chip architectures
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2009 (English)In: Journal of Low Power Electronics, ISSN 1546-1998, Vol. 5, no 3, 373-384 p.Article in journal (Refereed) Published
Abstract [en]

We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs. Differently from the most common approaches, which rely on Transaction-Level Modeling (TLM), we infer energy and performance figures directly from the Functional Untimed Level, by running the algorithmic specification natively on a common host machine. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 17% of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.

Place, publisher, year, edition, pages
2009. Vol. 5, no 3, 373-384 p.
Keyword [en]
Energy, High-level estimation, Performance
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-49322DOI: 10.1166/jolpe.2009.1037Scopus ID: 2-s2.0-72749093617OAI: oai:DiVA.org:kth-49322DiVA: diva2:459517
Note

QC 20111130

Available from: 2011-11-25 Created: 2011-11-25 Last updated: 2014-10-02Bibliographically approved

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Hemani, Ahmed

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