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Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2012 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, 1585-1591 p.Article in journal (Refereed) Published
Abstract [en]

The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

Place, publisher, year, edition, pages
2012. Vol. 59, no 6, 1585-1591 p.
Keyword [en]
Contact resistance, contact resistivity, cross-bridge Kelvin resistor (CBKR), cross Kelvin resistor (CKR)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-50123DOI: 10.1109/TED.2012.2189216ISI: 000304243600003Scopus ID: 2-s2.0-84861344938OAI: oai:DiVA.org:kth-50123DiVA: diva2:461075
Funder
Swedish Research CouncilEU, European Research Council, 228229StandUp
Note

QC 20120619. Updated from manuscript to article in journal.

Available from: 2011-12-02 Created: 2011-12-02 Last updated: 2017-12-08Bibliographically approved
In thesis
1. Fabrication, characterization, and modeling of metallic source/drain MOSFETs
Open this publication in new window or tab >>Fabrication, characterization, and modeling of metallic source/drain MOSFETs
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS).

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:15
Keyword
Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate, FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-49184 (URN)978-91-7501-161-5 (ISBN)
Public defence
2011-12-16, Sal / Hall C2, KTH-Electrum, Isafjordsgatan 26, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20111206Available from: 2011-12-06 Created: 2011-11-25 Last updated: 2011-12-06Bibliographically approved

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Hellström, Per-Erik

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