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A 32x32 smart photo-array with minimum-size FGMOS for amplification and FPN reduction
Physics Dept., Aristotle University of Thessaloniki, Greece.
Physics Dept., Aristotle University of Thessaloniki, Greece.
Physics Dept., Aristotle University of Thessaloniki, Greece.
2005 (English)In: SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, 2005, Vol. 2005, 199-203 p.Conference paper, Published paper (Refereed)
Abstract [en]

A logarithmic response photoarray, incorporating two minimum-sized floating-gate mosfets (FGMOS) in its basic photocell, is presented. Exploiting the same FGMOS as an analog memory element for Fixed Pattern Noise (FPN) reduction, and as an inherent amplifying element, is, to our knowledge, novel. The above features, favored by the use of small control gate capacitors, lead to area reduction. The circuit behavior is analyzed and experimental results of a 32×32 prototype array implemented in AMS 0.6Όm CMOS technology, are presented and discussed.

Place, publisher, year, edition, pages
2005. Vol. 2005, 199-203 p.
Keyword [en]
Capacitors, CMOS integrated circuits, Noise abatement, Photoelectric cells, Control gate capacitors, Fixed Pattern Noise (FPN), Floating-gate mosfets (FGMOS), Logarithmic response photoarrays, MOS devices
National Category
Signal Processing
Identifiers
URN: urn:nbn:se:kth:diva-51002DOI: 10.1109/SIPS.2005.1579864ISBN: 0780393341 (print)ISBN: 978-078039334-9 OAI: oai:DiVA.org:kth-51002DiVA: diva2:463151
Conference
SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation. Athens. 2 November 2005 - 4 November 2005
Note
QC 20111213Available from: 2011-12-08 Created: 2011-12-08 Last updated: 2011-12-13Bibliographically approved

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CiteExportLink to record
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  • apa
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