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A compact APS with FPN reduction and focusing criterion using FGMOS photocell
Physics Dept., Aristotle University of Thessaloniki, Greece.
Physics Dept., Aristotle University of Thessaloniki, Greece.
Physics Dept., Aristotle University of Thessaloniki, Greece.
2008 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, Vol. 147, no 2, 419-424 p.Article in journal (Refereed) Published
Abstract [en]

Prior implementations of CMOS photoarrays with floating-gate MOS (FGMOS), substituted one MOS with a FGMOS in, otherwise, well-established photocell structures. Bipolar manipulation of the floating-gate's charge requires special structures to achieve fixed pattern noise (FPN) suppression. The control capacitor accompanying the FGMOS, needed to be quite larger than the MOS parasitic capacitances, resulting in increased area. Also, output amplification was dealt separately, by additional amplification cells. The proposed logarithmic CMOS photoarray, carefully incorporates two FGMOS in each photocell, favoring the use of minimum control-gate capacitance, achieving area reduction. Unipolar manipulation of floating-gate charge is achieved without special circuitry, preserving FPN suppression. Simultaneously, output amplification is achieved by exploiting the same FGMOS's inherent processing capabilities. A very simple circuit providing a focusing function was also incorporated and successfully tested. Additionally, global normalization towards the average photocurrent, make the circuit ideal preprocessor for image recognition tasks. Experimental results from a 32 × 32 array in AMS 0.6 Όm CMOS technology support the theoretical analysis. © 2008 Elsevier B.V. All rights reserved.

Place, publisher, year, edition, pages
2008. Vol. 147, no 2, 419-424 p.
Keyword [en]
CMOS analog integrated circuits, Fixed pattern noise compensation, Floating-gate MOSFET, Logarithmic CMOS image sensors, Normalization, Canning, Capacitance, Electric currents, Electric network analysis, Image recognition, Photoelectric cells, Polarization, Semiconducting cadmium telluride, Area reduction, CMOS technologies, Fixed pattern noise, Floating gates, Focusing function, Gate capacitance, Global normalization, Parasitic capacitances, Pre processors, Processing capabilities, Recognition tasks, Theoretical analysis, Amplification
National Category
Signal Processing
URN: urn:nbn:se:kth:diva-50999DOI: 10.1016/j.sna.2008.05.009ISI: 000259685600010OAI: diva2:463153
QC 20111209Available from: 2011-12-08 Created: 2011-12-08 Last updated: 2011-12-09Bibliographically approved

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