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Method of joining components
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).ORCID iD: 0000-0001-9552-4234
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).ORCID iD: 0000-0002-0525-8647
2000 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.

Place, publisher, year, edition, pages
2000.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-51352OAI: oai:DiVA.org:kth-51352DiVA: diva2:463948
Patent
US 7067345 (2006-06-27)
Note

EP 1275146-B1 (2013-07-31)

Available from: 2011-12-12 Created: 2011-12-12 Last updated: 2013-08-07Bibliographically approved

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Authority records BETA

Stemme, GöranNiklaus, Frank

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