A reconfigurable successive approximation ADC in 0.18μm CMOS technology
2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008, IEEE conference proceedings, 2008, 646-649 p.Conference paper (Refereed)
This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level simulation results show that the ADC can achieve 28.9 dB SINAD at 66 MSPS in the UWB mode, and 53.9 dB SINAD at 1 MSPS in the Bluetooth mode.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2008. 646-649 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-58776DOI: 10.1109/ICECS.2008.4674936ScopusID: 2-s2.0-57849104117ISBN: 978-1-4244-2181-7OAI: oai:DiVA.org:kth-58776DiVA: diva2:473974
ICECS 2008. St. Julien's
QC 201201092012-01-082012-01-082012-01-09Bibliographically approved