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A reconfigurable successive approximation ADC in 0.18μm CMOS technology
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2008 (English)In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008, IEEE conference proceedings, 2008, 646-649 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level simulation results show that the ADC can achieve 28.9 dB SINAD at 66 MSPS in the UWB mode, and 53.9 dB SINAD at 1 MSPS in the Bluetooth mode.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2008. 646-649 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-58776DOI: 10.1109/ICECS.2008.4674936Scopus ID: 2-s2.0-57849104117ISBN: 978-1-4244-2181-7 (print)OAI: oai:DiVA.org:kth-58776DiVA: diva2:473974
Conference
ICECS 2008. St. Julien's
Note

QC 20120109

Available from: 2012-01-08 Created: 2012-01-08 Last updated: 2016-12-09Bibliographically approved

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Rusu, Ana

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Zhao, KangqiaoAmir, SaifullahMeng, XiaozhouAli, Muhammad MohsinGustafsson, MartinElnaggar, Mohammed IsmailRusu, Ana
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CiteExportLink to record
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Citation style
  • apa
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More styles
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  • de-DE
  • en-GB
  • en-US
  • fi-FI
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  • Other locale
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Output format
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