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Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
NUST Pakistan.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
NUST Pakistan.
2011 (English)In: 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, 2011, 60-65 p.Conference paper, Published paper (Refereed)
Abstract [en]

An efficient hardware implementation of Gaussian Random Number (GRN) generator based on Central Limit Theorem (CLT) is presented. CLT, although very simple to implement, is never used to generate high quality Gaussian numbers. This is due to the fact that direct implementation of CLT provides very poor accuracy in tail regions of the probability density function. In this work, we have shown that it is possible to achieve high tail accuracy by empirically computing the error in CLT, which can be compensated with a simple correction algorithm. The error has been modeled as first degree piece-wise polynomial approximation, using a novel non-uniform segmentation algorithm to compute the coefficients of polynomial segments. A novel hardware architecture of GRN generator is presented which requires only 420 slices and 1 DSP block of Xilinx Virtex-4 XC4VLX15 operating at 220 MHz. This resource utilization is better than any of the previously reported designs. Demonstrated for the tail accuracy of 6σ, the GRN generator design is scalable to achieve even higher accuracy with minimal increase in hardware resources. The accuracy of GRN generator is validated using statistical goodness of fit tests.

Place, publisher, year, edition, pages
2011. 60-65 p.
Keyword [en]
Gaussian random number;Xilinx Virtex-4 XC4VLX15 DSP block;central limit theorem;digital signal processor;nonuniform segmentation algorithm;piecewise polynomial approximation;polynomial segment;probability density function;simple correction algorithm;statistical goodness-of-fit tests;Gaussian processes;digital signal processing chips;polynomial approximation;random number generation;statistical analysis;
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:kth:diva-59194DOI: 10.1109/VLSISoC.2011.6081630Scopus ID: 2-s2.0-83755169570ISBN: 978-145770171-9 (print)OAI: oai:DiVA.org:kth-59194DiVA: diva2:475315
Conference
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. Kowloon. 3 October 2011 - 5 October 2011
Note
QC 20120113Available from: 2012-01-10 Created: 2012-01-10 Last updated: 2012-01-13Bibliographically approved

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Hemani, Ahmed

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  • apa
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