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Control Scheme for a CGRA
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
2010 (English)In: Proc. 22nd Int Computer Architecture and High Performance Computing (SBAC-PAD) Symp, 2010, 17-24 p.Conference paper (Refereed)
Abstract [en]

Ability to instantiate low cost and agile FSMs that can implement an arbitrary parallelism and combine such FSMs in a chain and in a hierarchy is one of the key differentiating factors between the ASICs and MPSOCs. CGRAs that have been reported in literature, like MPSOCs, also lack this ASIC like ability. The downside of ASICs is their lack of reuse and high engineering cost. We present a CGRA architecture that retains the programmability of CGRA and yet has the ASIC like ability to construct a) arbitrarily parallel data-path/FSM combine, b) chain an arbitrary number of such FSMs and c) create a hierarchy of such chains. We present in detail the architecture of such a control scheme and illustrate its use for an example composed of FFT and FIRs. We quantify the benefits of our approach by benchmarking for energy-delay product against a) ASICs (4.8X worse), b) a state-of-the-art CGRA (4.58X better) and FPGAs (63.95X better).

Place, publisher, year, edition, pages
2010. 17-24 p.
National Category
Embedded Systems
URN: urn:nbn:se:kth:diva-59186DOI: 10.1109/SBAC-PAD.2010.12ScopusID: 2-s2.0-78650753245ISBN: 978-076954216-4OAI: diva2:475330
22nd International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2010. Petropolis. 27 October 2010 - 30 October 2010
QC 20120112Available from: 2012-01-10 Created: 2012-01-10 Last updated: 2012-01-12Bibliographically approved

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Shami, Muhammad AliHemani, Ahmed
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