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A NoC based distributed memory architecture with programmable and partitionable capabilities
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
NIT,Trichy,India .
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010Conference paper, Published paper (Refereed)
Abstract [en]

The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.

Place, publisher, year, edition, pages
2010.
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-59224DOI: 10.1109/NORCHIP.2010.5669440Scopus ID: 2-s2.0-78751469007ISBN: 978-142448973-2 (print)OAI: oai:DiVA.org:kth-59224DiVA: diva2:475411
Conference
28th Norchip Conference, NORCHIP 2010. Tampere. 15 November 2010 - 16 November 2010
Note
QC 20120112Available from: 2012-01-10 Created: 2012-01-10 Last updated: 2012-01-12Bibliographically approved

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Hemani, Ahmed

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CiteExportLink to record
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Citation style
  • apa
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  • Other locale
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Output format
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