Design of a fault-tolerant coarse-grained reconfigurable architecture: A case study
2010 (English)In: Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010, 2010, 845-852 p.Conference paper (Refereed)
This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution of the last operation, once an error is detected. We have chosen the DART architecture as a vehicle to study the efficiency of this approach to protect its datapaths. Simulation results have confirmed hardware savings of the proposed approach over duplication.
Place, publisher, year, edition, pages
2010. 845-852 p.
Design; Embedded systems; Error detection
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-60682DOI: 10.1109/ISQED.2010.5450481ScopusID: 2-s2.0-77952618161ISBN: 978-142446455-5OAI: oai:DiVA.org:kth-60682DiVA: diva2:477728
11th International Symposium on Quality Electronic Design, ISQED 2010, San Jose, CA, 22-24 March, 2010
QC 201201182012-01-132012-01-132012-01-18Bibliographically approved