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Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2011 (English)In: Proc. IEEE Int Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) Symp, 2011, 290-293 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper considers the possibility of speeding up the configuration by reducing the size of configware in coarsegrained reconfigurable architectures (CGRAs). Our goal was to reduce the number of cycles and increase the configuration bandwidth. The proposed technique relies on multicasting and bitstream compression. The multicasting reduces the cycles by configuring the components performing identical functions simultaneously, in a single cycle, while the bitstream compression increases the configuration bandwidth. We have chosen the dynamically reconfigurable resource array (DRRA) architecture as a vehicle to study the efficiency of this approach. In our proposed method, the configuration bitstream is compressed offline and stored in a memory. If reconfiguration is required, the compressed bitstream is decompressed using an online decompresser and sent to DRRA. Simulation results using practical applications showed upto 78% and 22% decrease in configuration cycles for completely parallel and completely serial implementations, respectively. Synthesis results have confirmed nigligible overhead in terms of area (1.2 %) and timing.

Place, publisher, year, edition, pages
2011. 290-293 p.
Keyword [en]
Bit stream, Bitstream compression, Coarse grained reconfigurable architecture, Configuration bitstream, Configuration mechanisms, Configware, Number of cycles, Offline, Re-configurable, Single cycle
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-60681DOI: 10.1109/IPDPS.2011.166Scopus ID: 2-s2.0-83455263906ISBN: 9780769543857 (print)OAI: oai:DiVA.org:kth-60681DiVA: diva2:477729
Conference
25th IEEE International Parallel and Distributed Processing Symposium, Workshops and Phd Forum, IPDPSW 2011, Anchorage, AK, 16-20 May, 2011
Note

QC 20120118

Available from: 2012-01-13 Created: 2012-01-13 Last updated: 2017-02-24Bibliographically approved

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Hemani, Ahmed

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