Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs
2010 (English)In: Proceedings of Design Automation and Test in Europe (DATE ’10), 2010, 1035-1040 p.Conference paper (Refereed)
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.
Place, publisher, year, edition, pages
2010. 1035-1040 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-62096ScopusID: 2-s2.0-77953095861ISBN: 978-398108016-2OAI: oai:DiVA.org:kth-62096DiVA: diva2:479804
Design, Automation and Test in Europe Conference and Exhibition, DATE 2010. Dresden. 8 March 2010 - 12 March 2010
QC 201201202012-01-182012-01-182012-01-20Bibliographically approved