Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip
2009 (English)In: DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, 119-122 p.Conference paper (Refereed)
We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.
Place, publisher, year, edition, pages
2009. 119-122 p.
Cache coherence, Hierarchical directory, Network cluster, Network-on-Chip
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-62093DOI: 10.1109/DTIS.2009.4938037ISI: 000269052000021ScopusID: 2-s2.0-67650364848OAI: oai:DiVA.org:kth-62093DiVA: diva2:479809
4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era. Cairo, EGYPT. APR 06-07, 2009
QC 201201192012-01-182012-01-182012-01-19Bibliographically approved