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Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2009 (English)In: DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, 119-122 p.Conference paper, Published paper (Refereed)
Abstract [en]

We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.

Place, publisher, year, edition, pages
2009. 119-122 p.
Keyword [en]
Cache coherence, Hierarchical directory, Network cluster, Network-on-Chip
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62093DOI: 10.1109/DTIS.2009.4938037ISI: 000269052000021Scopus ID: 2-s2.0-67650364848OAI: oai:DiVA.org:kth-62093DiVA: diva2:479809
Conference
4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era. Cairo, EGYPT. APR 06-07, 2009
Note

QC 20120119

Available from: 2012-01-18 Created: 2012-01-18 Last updated: 2016-12-19Bibliographically approved

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Lu, Zhonghai

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Zhang, YuangLu, ZhonghaiJantsch, AxelLi, LiGao, Minglun
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