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Hardware/Software Co-design of an ATCA-based Computation Platform for Data Acquisition and Triggering
KTH, School of Information and Communication Technology (ICT). (Electronic Systems)
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2009 (English)In: 16th IEEE NPSS Real Time Conference, 2009, 485-489 p.Conference paper, Published paper (Refereed)
Abstract [en]

An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such its PANDA. HADES, and BESIII. Each Compute Node (CN) appears as one (if the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Clips inter-FPGA on-board channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet. 140 GBytes DDR2 SDRAM. and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to (the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design. application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.

Place, publisher, year, edition, pages
2009. 485-489 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62088DOI: 10.1109/RTC.2009.5321538ISI: 000275741600096Scopus ID: 2-s2.0-72749090837ISBN: 978-1-4244-5796-0 (print)OAI: oai:DiVA.org:kth-62088DiVA: diva2:479812
Note
QC 20120119Available from: 2012-01-18 Created: 2012-01-18 Last updated: 2012-01-19Bibliographically approved

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Publisher's full textScopushttp://web.it.kth.se/~axel/papers/2009/RT-MingLiu-Codesign.pdf

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CiteExportLink to record
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  • apa
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