All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator
2011 (English)In: Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, IEEE , 2011, 1-4 p.Conference paper (Refereed)
A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.
Place, publisher, year, edition, pages
IEEE , 2011. 1-4 p.
, IEEE, ISSN 1529-2517
ADPLL, All digital, Delta Sigma, polar transmitter, transmitter
IdentifiersURN: urn:nbn:se:kth:diva-62144DOI: 10.1109/RFIC.2011.5940595ScopusID: 2-s2.0-79960766547ISBN: 978-1-4244-8293-1OAI: oai:DiVA.org:kth-62144DiVA: diva2:479877
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
ProjectsiPack Vinn Excellence Center
QC 201202012012-02-152012-01-182013-02-28Bibliographically approved