Design space exploration for field programmable compressor trees
2008 (English)In: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, New York: ACM Press, 2008, 207-216 p.Conference paper (Refereed)
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor’s largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.
Place, publisher, year, edition, pages
New York: ACM Press, 2008. 207-216 p.
, CASES ’08
design space exploration (dse), field programmable compressor tree (fpct)
IdentifiersURN: urn:nbn:se:kth:diva-62161DOI: 10.1145/1450095.1450126ScopusID: 2-s2.0-63349107951OAI: oai:DiVA.org:kth-62161DiVA: diva2:479902
Embedded Systems Week 2008 - 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08;Atlanta, GA;19 October 2008 through 24 October 2008
Qc 201202012012-02-012012-01-182012-03-22Bibliographically approved