Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
2009 (English)In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, San Francisco: IEEE conference proceedings, 2009, 345-351 p.Conference paper (Refereed)
The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
Place, publisher, year, edition, pages
San Francisco: IEEE conference proceedings, 2009. 345-351 p.
cycle-accurate RTL simulator;horizontal network link;multiclock 3-dimensional network-on-chip mesh architecture;on-chip interconnect;physical mapping;switches;system-level impact;through silicon vias;vertical network link;integrated circuit interconnections;network analysis;network-on-chip;
IdentifiersURN: urn:nbn:se:kth:diva-62170DOI: 10.1109/3DIC.2009.5306540ISI: 000275055600063ScopusID: 2-s2.0-70549103317ISBN: 978-1-4244-4511-0OAI: oai:DiVA.org:kth-62170DiVA: diva2:479916
IEEE International Conference on 3D Systems Integration, San Francisco, CA, SEP 28-30, 2009
QC 201201202012-01-182012-01-182012-03-22Bibliographically approved