Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Memory Architecture and Management in an NoC Platform
KTH, School of Information and Communication Technology (ICT), Electronic Systems. (School of Information and Communication Technology (ICT))
KTH, School of Information and Communication Technology (ICT), Electronic Systems. (School of Information and Communication Technology (ICT))
KTH, School of Information and Communication Technology (ICT), Electronic Systems. (School of Information and Communication Technology (ICT))
KTH, School of Information and Communication Technology (ICT), Electronic Systems. (School of Information and Communication Technology (ICT))
Show others and affiliations
2011 (English)In: Scalable Multi-core Architectures: Design Methodologies and Tools / [ed] Axel Jantsch and Dimitrios Soudris, Springer, 2011, 1, p. 3-28Chapter in book (Refereed)
Abstract [en]

The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME’s main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.

Place, publisher, year, edition, pages
Springer, 2011, 1. p. 3-28
Keywords [en]
Network on Chip, SoC Architecture, Memory Organization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62158ISBN: 9781441967770 (print)OAI: oai:DiVA.org:kth-62158DiVA, id: diva2:479924
Projects
MOSART
Note
QC 20120110Available from: 2012-01-20 Created: 2012-01-18 Last updated: 2013-02-04Bibliographically approved
In thesis
1. Architecture Support and Scalability Analysis of Memory Consistency Models in Network-on-Chip based Systems
Open this publication in new window or tab >>Architecture Support and Scalability Analysis of Memory Consistency Models in Network-on-Chip based Systems
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The shared memory systems should support parallelization at the computation (multi-core), communication (Network-on-Chip, NoC) and memory architecture levels to exploit the potential performance benefits. These parallel systems supporting shared memory abstraction both in the general purpose and application specific domains are confronting the critical issue of memory consistency. The memory consistency issue arises due to the unconstrained memory operations which leads to the unexpected behavior of shared memory systems. The memory consistency models enforce ordering constraints on the memory operations for the expected behavior of the shared memory systems. The intuitive Sequential Consistency (SC) model enforces strict ordering constraints on the memory operations and does not take advantage of the system optimizations both in the hardware and software. Alternatively, the relaxed memory consistency models relax the ordering constraints on the memory operations and exploit these optimizations to enhance the system performance at the reasonable cost. The purpose of this thesis is twofold. First, the novel architecture supports are provided for the different memory consistency models like: SC, Total Store Ordering (TSO), Partial Store Ordering (PSO), Weak Consistency (WC), Release Consistency (RC) and Protected Release Consistency (PRC) in the NoC-based multi-core (McNoC) systems. The PRC model is proposed as an extension of the RC model which provides additional reordering and relaxation in the memory operations. Second, the scalability analysis of these memory consistency models is performed in the McNoC systems.

The architecture supports for these different memory consistency models are provided in the McNoC platforms. Each configurable McNoC platform uses a packet-switched 2-D mesh NoC with deflection routing policy, distributed shared memory (DSM), distributed locks and customized processor interface. The memory consistency models/protocols are implemented in the customized processor interfaces which are developed to integrate the processors with the rest of the system. The realization schemes for the memory consistency models are based on a transaction counter and an an an address ddress ddress ddress ddress ddress ddress stack tacktack-based based based based based based novel approaches.approaches.approaches.approaches. approaches.approaches.approaches.approaches.approaches.approaches. The transaction counter is used in each node of the network to keep track of the outstanding memory operations issued by a processor in the system. The address stack is used in each node of the network to keep track of the addresses of the outstanding memory operations issued by a processor in the system. These hardware structures are used in the processor interface to enforce the required global orders under these different memory consistency models. The realization scheme of the PRC model in addition also uses acquire counter for further classification of the data operations as unprotected and protected operations.

The scalability analysis of these different memory consistency models is performed on the basis of different workloads which are developed and mapped on the various sized networks. The scalability study is conducted in the McNoC systems with 1 to 64-cores with various applications using different problem sizes and traffic patterns. The performance metrics like execution time, performance, speedup, overhead and efficiency are evaluated as a function of the network size. The experiments are conducted both with the synthetic and application workloads. The experimental results under different application workloads show that the average execution time under the relaxed memory consistency models decreases relative to the SC model. The specific numbers are highly sensitive to the application and depend on how well it matches to the architectures. This study shows the performance improvement under the relaxed memory consistency models over the SC model that is dependent on the computation-to-communication ratio, traffic patterns, data-to-synchronization ratio and the problem size. The performance improvement of the PRC and RC models over the SC model tends to be higher than 50% as observed in the experiments, when the system is further scaled up.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. p. xviii, 143
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 12:11
Keywords
Memory consistency, Protected release consistency, Distributed shared memory; Network-on-Chip, Scalability
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-117700 (URN)978-91-7501-617-7 (ISBN)
Public defence
2013-03-13, Sal E, Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Note

QC 20130204

Available from: 2013-02-04 Created: 2013-02-02 Last updated: 2013-02-04Bibliographically approved

Open Access in DiVA

MOSART Book Chapter1(778 kB)899 downloads
File information
File name FULLTEXT01.pdfFile size 778 kBChecksum SHA-512
638daa21a50fb05b1a96591f8f051d50600bccf007f566ceb20eaa5f95a26612c03352625de6d8ac175fb36877046d964f0918a37c75eb14fe5aa62ac5f7eb33
Type fulltextMimetype application/pdf

Other links

http://www.bokus.com/bok/9781441967770/scalable-multi-core-architectures/The final publication is available at www.springerlink.com

Authority records BETA

Lu, Zhonghai

Search in DiVA

By author/editor
Jantsch, AxelChen, XiaowenNaeem, AbdulZhang, YuangPenolazzi, SandroLu, Zhonghai
By organisation
Electronic Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 899 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 604 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf