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Shared Memory Consistency Models Evaluation in NoC based Multicore Systems
KTH, School of Information and Communication Technology (ICT), Electronic Systems. (School of Information and Communication Technology (ICT))
2012 (English)In: Design, Automation and Test in Europe (DATE 2012), PhD Forum, Dresden, Dermany: EDAA / ACM SIGDA , 2012Conference paper, Published paper (Refereed)
Abstract [en]

This paper overviews our study on various shared memory consistency models, Sequential Consistency (SC), Weak Consistency (WC), Release Consistency (RC), and Protected Release Consistency (PRC) models in Network-on-Chip (NoC) based Distributed Shared Memory (DSM) multi-core systems. These memory models are implemented by using a transaction counter (TC) based unified approach in the NoC based systems. The performance gain observed in the WC, RC and PRC relaxed memory models under various benchmarks is between 20% and 50% compared to the SC strict model.

Place, publisher, year, edition, pages
Dresden, Dermany: EDAA / ACM SIGDA , 2012.
Keyword [en]
Network-on-Chip, Distributed shared memory, Memory consistency, Protected release consistency, Scalability
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62191OAI: oai:DiVA.org:kth-62191DiVA: diva2:479954
Conference
Design, Automation and Test in Europe (DATE 2012), 12-16 March Dresden, Germany
Note
QSAvailable from: 2012-02-29 Created: 2012-01-18 Last updated: 2012-02-29Bibliographically approved

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf