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A 5Mgate/414mW Networked Media SoC in 0.13um CMOS with 720p Multi-Standard Video Decoding
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0002-7589-9749
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2009 (English)In: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), IEEE Solid-State Circuits Society, 2009, 385-388 p.Conference paper, Published paper (Refereed)
Abstract [en]

A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet network interface and coarse-grained configurable video decoding unit. Real-time 1280x720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with core size of 6.4mm * 6.4mm. To achieve low power design, flexible power management strategy is implemented for dynamically control of computational capabilities with various workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280x720@25fps) video streams are decoded. When the SoC decodes real-time CIF (352x288@25fps) video streams, it requires 27MHz system frequency and consumes 95mW.

Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2009. 385-388 p.
Series
IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62206DOI: 10.1109/ASSCC.2009.5357177ISI: 000298194200097Scopus ID: 2-s2.0-76249116270ISBN: 978-1-4244-4434-2 (print)OAI: oai:DiVA.org:kth-62206DiVA: diva2:479957
Conference
“”, IEEE Asian Solid-State Circuits Conference (ASSCC), Taipei, TAIWAN, NOV 16-18, 2009
Note
QC 20120224Available from: 2012-01-18 Created: 2012-01-18 Last updated: 2015-10-09Bibliographically approved
In thesis
1. Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
Open this publication in new window or tab >>Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency.

To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs.

Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW.

When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes.

In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 74 p.
Series
TRITA-ICT, ISSN 1653-6363 ; 15:11
National Category
Computer Systems
Identifiers
urn:nbn:se:kth:diva-174896 (URN)978-91-7595-692-3 (ISBN)
Public defence
2015-11-04, Sal B, Electrum 229, Kista, 10:00 (English)
Opponent
Supervisors
Funder
VINNOVA
Note

QC 20151009

Available from: 2015-10-09 Created: 2015-10-08 Last updated: 2015-10-09Bibliographically approved

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Ma, Ning

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