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Bandwidth Optimization for Through Silicon Via(TSV) bundles in 3D Integrated Circuits
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2009 (English)In: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France: DATE Conference , 2009, 283-287 p.Conference paper, Published paper (Refereed)
Abstract [en]

Through silicon vias (TSVs) are the backbone of 3D integration technology connecting vertically stacked ICs. Parallel TSVs in the form of bundles are used for vertical signaling.In this paper, we present the ways of maximizing the total bandwidth of a TSV bundle placed in a fixed area by varying the density and the geometries. The ways of optimizing the total bandwidth using analytical methods fora bundle of TSVs placed in a structure with a fixed area and length are examined. The result shows that for uniformly distributed TSVs, maximum bandwidth by proportionalplacement of fewer number of TSV in the bundle can be achieved.

Place, publisher, year, edition, pages
Nice, France: DATE Conference , 2009. 283-287 p.
Keyword [en]
TSV bandwidth, 3D integration, TSV RC model
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-62183OAI: oai:DiVA.org:kth-62183DiVA: diva2:480055
Conference
DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test. Nice, France. April 24, 2009
Projects
EU-FP7 ELITE-215030
Note

QC 20120119. QC 20160209

Available from: 2012-01-18 Created: 2012-01-18 Last updated: 2016-02-09Bibliographically approved
In thesis
1. Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
Open this publication in new window or tab >>Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.

First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.

Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.

Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.

The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. xviii, 80 p.
Series
TRITA-ICT, 2015:29
Keyword
Alpha-model, Average distance, B-Model, NoC, Zero-load predictive model, deflection routing, q-routing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-179694 (URN)978-91-7595-803-3 (ISBN)
Public defence
2016-01-20, Hall C, Electrum, Isafjordsgatan 26, 16440, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20151221

Available from: 2015-12-21 Created: 2015-12-21 Last updated: 2015-12-21Bibliographically approved

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