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Extending Platform-Based Design to Network on Chip Systems
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
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2003 (English)In: Proceedings of the International Conference on VLSI Design, 2003Conference paper, Published paper (Refereed)
Abstract [en]

Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased-systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.

Place, publisher, year, edition, pages
2003.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62081OAI: oai:DiVA.org:kth-62081DiVA: diva2:481108
Conference
International Conference on VLSI Design, 2003
Note

QC 20121121

Available from: 2012-01-20 Created: 2012-01-18 Last updated: 2012-11-21Bibliographically approved

Open Access in DiVA

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Other links

http://www.imit.kth.se/~axel/papers/2003/VLSI-Soininen.pdf
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Microelectronics and Information Technology, IMIT
Electrical Engineering, Electronic Engineering, Information Engineering

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