Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations
2010 (English)In: Proceedings of the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip, 2010, 149-152 p.Conference paper (Refereed)
Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most straightforward way is to increase the reconfiguration throughput, as many previous contributions did. In addition to shortening FPGA reconfiguration time, we introduce a new concept of Virtual ConFigurations (VCF) in this paper, hiding dynamic reconfiguration time in the background to reduce the overhead. Experimental results demonstrate up to 29.9% throughput enhancement by adopting two VCFs in a consumerreconfigurable design. The packet latency performance is also largely improved by extending the channel saturation to a higher packet injection rate.
Place, publisher, year, edition, pages
2010. 149-152 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63741ScopusID: 2-s2.0-84883209870ISBN: 978-386644515-4OAI: oai:DiVA.org:kth-63741DiVA: diva2:482514
5th International Workshop on Reconfigurable Communication-Centric Systems on Chip 2010, ReCoSoC 2010; Karlsruhe; Germany; 17 May 2010 through 19 May 2010
QC 201204242012-01-242012-01-242014-08-15Bibliographically approved