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Inter-process communication using pipes in FPGA-based adaptive computing
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 80-85 p.Conference paper, Published paper (Refereed)
Abstract [en]

In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable region. In this paper, we use pipes for IPC and analyze the performance in terms of throughput, throughput efficiency and latency in switching contexts. We also present two practical implementations using FPGA BRAM and external DDR memory. Experimental results expose the key role that context switching plays in determining the IPC performance at various pipe sizes and data rates.

Place, publisher, year, edition, pages
2010. 80-85 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63742DOI: 10.1109/ISVLSI.2010.103Scopus ID: 2-s2.0-77957899343ISBN: 978-076954076-4 (print)OAI: oai:DiVA.org:kth-63742DiVA: diva2:482515
Conference
IEEE Annual Symposium on VLSI, ISVLSI 2010; Lixouri, Kefalonia; 5 July 2010 through 7 July 2010
Note
QC 20120208Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-02-08Bibliographically approved

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Lu, Zhonghai

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  • apa
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  • Other locale
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Output format
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