A Reconfigurable Design Framework for FPGA Adaptive Computing
2009 (English)In: 2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS, IEEE , 2009, 439-444 p.Conference paper (Refereed)
Partial Reconfiguration (PR) offers the possibility to adaptively change part of the FPGA design without stopping the remaining system. In this paper, we present a comprehensive framework for adaptive computing, in which design key points of hardware processes, system interconnections, Operating Systems (OS), device drivers, scheduler software as well as context switching are respectively concerned in different hardware/software layers. A case study is discussed to demonstrate an example of swapping a Flash memory controller and an SRAM controller in response to diverse memory access needs. Result analysis reveals a more efficient resource utilization of 52.1% I/O pads, 86.5% LUTs and 81.3% Flip-Flops, when compared to the static design with same functionalities. A small reconfiguration overhead of context switching is measured within the range from hundreds of microseconds to milliseconds. Moreover, technical perspectives are analyzed and it is foreseen to obtain great benefits with the proposed design framework in object applications of particle physics experiments.
Place, publisher, year, edition, pages
IEEE , 2009. 439-444 p.
adaptive computing, partial reconfiguration, hardware process scheduling, hardware context switching
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63743DOI: 10.1109/ReConFig.2009.39ISI: 000285022700075ScopusID: 2-s2.0-77950467755ISBN: 978-1-4244-5293-4OAI: oai:DiVA.org:kth-63743DiVA: diva2:482516
2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09; Cancun; 9 December 2009 through 11 December 2009
QC 201202082012-01-242012-01-242012-03-29Bibliographically approved