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Trigger algorithm development on FPGA-based Compute Nodes
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2009 (English)In: 2009 16th IEEE-NPSS Real Time Conference, New York: IEEE , 2009, 478-484 p.Conference paper, Published paper (Refereed)
Abstract [en]

Based on the ATCA computation architecture and Compute Nodes (CN), investigation and implementation work has been being executed for HADES and PANDA trigger algorithms. We present our designs for HADES track reconstruction processing, Cherenkov ring recognition, Time-Of-Flight processing, electromagnetic shower recognition.. and the PANDA straw tube tracking algorithm. They will appear as co-processors in the uniform system design to undertake the detector-specific computing. The algorithm principles will be explained and hardware designs are described in the paper. The current progress reveals the feasibility to implement these algorithms on FPGAs. Also experimental results demonstrate the performance speedup when compared to alternative software solutions, as well as the potential capability of high-speed parallel/pipelined processing in Data Acquisition and Trigger systems.

Place, publisher, year, edition, pages
New York: IEEE , 2009. 478-484 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63732DOI: 10.1109/RTC.2009.5321547ISI: 000275741600095Scopus ID: 2-s2.0-72749109130ISBN: 978-1-4244-5796-0 (print)OAI: oai:DiVA.org:kth-63732DiVA: diva2:482527
Conference
2009 16th IEEE-NPSS Real Time Conference; Beijing; 10 May 2009 through 15 May 2009
Note
QC 20120208Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-02-08Bibliographically approved

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Lu, Zhonghai

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CiteExportLink to record
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