Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
2009 (English)In: FPL 09: 19th International Conference on Field Programmable Logic and Applications / [ed] Danek, M; Kadlec, J, 2009, 498-502 p.Conference paper (Refereed)
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we discuss multiple design architectures and thoroughly investigate their performance with measurements for different partial bitstream sizes. Compared to the reference OPB_HWICAP and XPS_HWICAP designs, experimental results show that DMA_HWICAP and MST_HWICAP reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. The BRAM_HWICAP design can even approach the reconfiguration speed limit of the ICAP primitive at the cost of large Block RAM utilization.
Place, publisher, year, edition, pages
2009. 498-502 p.
, International Conference on Field Programmable Logic and Applications, ISSN 1946-1488
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63734DOI: 10.1109/FPL.2009.5272463ISI: 000277506300081ScopusID: 2-s2.0-70449922693ISBN: 978-1-4244-3891-4OAI: oai:DiVA.org:kth-63734DiVA: diva2:482529
FPL 09: 19th International Conference on Field Programmable Logic and Applications; Prague; 31 August 2009 through 2 September 2009
QC 201202082012-01-242012-01-242012-02-08Bibliographically approved