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A Framework for Designing Congestion-Aware Deterministic Routing
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2010 (English)In: NoCArc '10 Proceedings of the Third International Workshop on Network on Chip Architectures, 2010, 45-50 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present a system-level Congestion-Aware Routing (CAR) framework for designing minimal deterministic routing algorithms. CAR exploits the peculiarities of the application workload to spread the load evenly across the network. To this end, we first formulate an optimization problem of minimizing the level of congestion in the network and then use the simulated annealing heuristic to solve this problem. The proposed framework assures deadlock-free routing, even in the networks without virtual channels. Experiments with both synthetic and realistic workloads show the effectiveness of the CAR framework. Results show that maximum sustainable throughput of the network is improved by up to 205% for different applications and architectures.

Place, publisher, year, edition, pages
2010. 45-50 p.
Keyword [en]
Algorithms, C.2.1 [Network Architecture and Design], Network communications, Design, Performance
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63728DOI: 10.1145/1921249.1921261Scopus ID: 2-s2.0-79951614608ISBN: 978-145030397-2 (print)OAI: oai:DiVA.org:kth-63728DiVA: diva2:482535
Conference
3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43; Atlanta, GA; 4 December 2010 through 4 December 2010
Note

QC 20120203

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2013-12-05Bibliographically approved
In thesis
1. Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
Open this publication in new window or tab >>Performance Analysis and Design Space Exploration of On-Chip Interconnection Networks
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The advance of semiconductor technology, which has led to more than one billion transistors on a single chip, has enabled designers to integrate dozens of IP (intellectual property) blocks together with large amounts of embedded memory. These advances, along with the fact that traditional communication architectures do not scale well have led to significant changes in the architecture and design of integrated circuits. One solution to these problems is to implement such a complex system using an on-chip interconnection network or network-on-chip (NoC). The multiple concurrent connections of such networks mean that they have extremely high bandwidth. Regularity can lead to design modularity providing a standard interface for easier component reuse and improved interoperability.

The present thesis addresses the performance analysis and design space exploration of NoCs using analytical and simulation-based performance analysis approaches. At first, we developed a simulator aimed to performance analysis of interconnection networks. The simulator is then used to evaluate the performance of networks topologies and routing algorithms since their choice heavily affect the performance of NoCs. Then, we surveyed popular mathematical formalisms – queueing theory, network calculus, schedulability analysis, and dataflow analysis – and how they have been applied to the analysis of on-chip communication performance in NoCs. We also addressed research problems related to modelling and design space exploration of NoCs.

In the next step, analytical router models were developed that analyse NoC performance. In addition to providing aggregate performance metrics such as latency and throughput, our approach also provides feedback about the network characteristics at a fine-level of granularity. Our approach explicates the impact that various design parameters have on the performance, thereby providing invaluable insight into NoC design. This makes it possible to use the proposed models as a powerful design and optimisation tool.

We then used the proposed analytical models to address the design space exploration and optimisation problem. System-level frameworks to address the application mapping and to design routing algorithms for NoCs were presented. We first formulated an optimisation problem of minimizing average packet latency in the network, and then solved this problem using the simulated annealing heuristic. The proposed framework can also address other design space exploration problems such as topology selection and buffer dimensioning.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xxi, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:21
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-136409 (URN)978-91-7501-923-9 (ISBN)
Public defence
2013-12-18, Sal/Hall D, Forum, KTH-ICT, Isafjordsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20131205

Available from: 2013-12-05 Created: 2013-12-05 Last updated: 2013-12-05Bibliographically approved

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Lu, Zhonghai

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