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A Case Study on Hardware/Software Partitioning
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0002-8072-1742
1994 (English)In: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, IEEE conference proceedings, 1994, 111-118 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.

Place, publisher, year, edition, pages
IEEE conference proceedings, 1994. 111-118 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63701DOI: 10.1109/FPGA.1994.315586ISBN: 0-8186-5490-2 (print)OAI: oai:DiVA.org:kth-63701DiVA: diva2:482564
Conference
IEEE Workshop on FPGAs for Custom Computing Machines, Napa Valley, CA, 10 Apr 1994-13 Apr 1994
Note

QC 20121121

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-11-21Bibliographically approved

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֖berg, Johnny

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