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Optimal Regulation of Traffic Flows in Networks-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic Systems. Ferdowsi University of Mashhad, Iran .
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Ferdowsi Univ Mashhad, Dept Comp, Fac Engn, Mashhad, Iran.
2010 (English)In: Proceedings of the Design Automation and Test Europe Conference (DATE), IEEE Computer Society, 2010, 1621-1624 p.Conference paper, Published paper (Refereed)
Abstract [en]

We have proposed (σ, ρ)-based flow regulation to reduce delay and backlog bounds in SoC architectures, where σ bounds the traffic burstiness and ρ the traffic rate. The regulation is conducted per-flow for its peak rate and traffic burstiness. In this paper, we optimize these regulation parameters in networks on chips where many flows may have conflicting regulation requirements. We formulate an optimization problem for minimizing total buffers under performance constraints. We solve the problem with the interior point method. Our case study results exhibit 48% reduction of total buffers and 16% reduction of total latency for the proposed problem. The optimization solution has low run-time complexity, enabling quick exploration of large design space.

Place, publisher, year, edition, pages
IEEE Computer Society, 2010. 1621-1624 p.
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keyword [en]
Flow regulation, In-network, Interior point methods, Large designs, Optimization problems, Optimization solution, Performance constraints, Runtimes, SoC architecture, Traffic burstiness, Traffic flow, Traffic rate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63677Scopus ID: 2-s2.0-77953098329ISBN: 978-398108016-2 (print)OAI: oai:DiVA.org:kth-63677DiVA: diva2:482594
Conference
DATE '10, Conference on Design, Automation and Test in Europe. Dresden, Germany. 8-12 March 2010
Note

QC 20120425

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2015-03-10Bibliographically approved
In thesis
1. Analysis and Management of Communication in On-Chip Networks
Open this publication in new window or tab >>Analysis and Management of Communication in On-Chip Networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Regarding the needs of low-power, high-performance embedded systems and the growing computation-intensive applications, the number of computing resources in a single chip has enormously increased. The current VLSI technology is able to support such an integration of transistors and add many computing resources such as CPU, DSP, specific IPs, etc to build a Systemon- Chip (SoC). However, interconnection between resources becomes another challenging issue which can be raised by using an on-chip interconnection network or Network-on-Chip (NoC). NoC-based communication which allows pipelined concurrent transmissions of transactions is becoming a dominate infrastructure for many core computing platforms.

This thesis analyzes and manages both Best Effort (BE) and Guaranteed Service (GS) communications using analytical performance approaches. As the first step, the present thesis focuses on the flow control for BE traffic in NoC. It models BE source rates as the solution to a utility-based optimization problem which is constrained with link capacities while preserving GS traffic requirements at the desired level. Towards this, several utility functions including proportionally-fair, rate-sum, and max-min fair scenarios are investigated. Moreover, it is worth looking into a scenario in which BE source rates are determined in favor of minimizing the delay of such traffics. The presented flow control algorithms solve the proposed optimization problems determining injection rate in each BE source node.

In the next step, real-time systems with guaranteed service are considered. Real-time applications require performance guarantees even under worst-case conditions, i.e. Quality of Service (QoS). Using network calculus, we present and prove the required theorems for deriving performance metrics and then apply them to propose formal approaches for the worst-case performance analysis. The proposed analytical model is used to minimize total cost in the networks in terms of buffer and delay. To this end, we address several optimization problems and solve them to consider the impact of various objective functions. We also develop a tool which derives performance metrics for a given NoC, formulates and solves the considerable optimization problems to provide an invaluable insight for NoC designers.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xxi, 59 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-161178 (URN)978-91-7595-458-5 (ISBN)
Public defence
2015-03-30, Sal/hall C, Elektrum , KTH-ICT, Isafjordsgatan, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150310

Available from: 2015-03-10 Created: 2015-03-09 Last updated: 2015-03-10Bibliographically approved

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Lu, Zhonghai

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