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Network-on-Chip Multicasting with Low Latency Path Setup
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2011 (English)In: Proceedings of the VLSI-SoC Conference, 2011Conference paper, Published paper (Refereed)
Abstract [en]

A low-latency path setup approach with multiple setup packets for parallel set is presented. It reduces the header overhead compared to multiaddress encoding. Further, we propose four variants of deadlock-free multicast routing algorithms using different subpath generation methods, different destination partitioning, and channel sharing strategies. Experimental results show that the quatuor partitions path-like tree outperforms other algorithms.

Place, publisher, year, edition, pages
2011.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63674DOI: 10.1109/VLSISoC.2011.6081594Scopus ID: 2-s2.0-83755172201OAI: oai:DiVA.org:kth-63674DiVA: diva2:482674
Conference
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
Note
QC 20120209Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-02-09Bibliographically approved

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Lu, Zhonghai

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