Network-on-Chip Multicasting with Low Latency Path Setup
2011 (English)In: Proceedings of the VLSI-SoC Conference, 2011Conference paper (Refereed)
A low-latency path setup approach with multiple setup packets for parallel set is presented. It reduces the header overhead compared to multiaddress encoding. Further, we propose four variants of deadlock-free multicast routing algorithms using different subpath generation methods, different destination partitioning, and channel sharing strategies. Experimental results show that the quatuor partitions path-like tree outperforms other algorithms.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63674DOI: 10.1109/VLSISoC.2011.6081594ScopusID: 2-s2.0-83755172201OAI: oai:DiVA.org:kth-63674DiVA: diva2:482674
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
QC 201202092012-01-242012-01-242012-02-09Bibliographically approved